What you'll be doing:
Develop and maintain design automation and methodologies for SoC and networking clock flows.
Collaborate with design, STA, and project teams to ensure timely and high-quality design closure.
Develop and improve SoC top-level automation scripts and flows built upon existing infrastructure and tools.
Support SoC integration and construction flow activities across multiple projects.
Assist in timing, power, and noise analysis to ensure efficient performance.
What we need to see:
B.Sc. or M.Sc. in Electrical or Computer Engineering, or relevant professional experience.
At least 2 years of confirmed experience in SoC design, design automation, or methodology development.
Strong programming or scripting skills in at least one language (Python preferred; Perl, Tcl, or Make are advantages).
Understanding of physical design concepts including placement, routing, timing closure, and ECO implementation.
Familiarity with EDA tools for synthesis, place-and-route, and timing analysis (Synopsys or Cadence flows).
Strong analytical, problem-solving, and soft skills.
Way to stand out from the crowd:
Experience developing or maintaining SoC design or automation flows.
Knowledge of timing-related analysis (crosstalk, noise, delay).
Background in power or timing optimization techniques.
Collaborative attitude with the ability to work effectively across multi-functional teams.
Self-motivated and eager to learn while improving existing design flows.
