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This position is also well-suited for Analog Layout Engineers who are interested in transitioning into photonic integrated circuit (PIC) design.

In this role, you will be responsible for creating, optimizing and validating PIC layouts, ensuring manufacturability, performance and compliance with foundry design rules.

You will work closely with device designers, process engineers and tape-out teams to deliver high-quality layouts of silicon photonics PICs.

Strong candidates will have hands-on experience with industry-standard layout tools, especially Cadence Virtuoso or similar software.

Understanding of photonic components, waveguide routing and automated layout generation is a major advantage.

You will also contribute to layout methodologies, PCells, and design automation flows to accelerate PIC development.

Responsibilities

Develop and implement mask layouts for photonic integrated circuits using Cadence Virtuoso or similar software.

Create and maintain PCells for photonic building blocks (waveguides, couplers, modulators, gratings, etc.).

Perform waveguide routing, ensuring correct connectivity, bend radius limits, and low-loss optical paths.

Verify layouts using DRC, and LVS to ensure compliance with foundry requirements.

Collaborate with device designers to translate basic schematics and specifications into Software schematics and manufacturable layouts.

Optimize layouts for performance, yield, and compactness while adhering to technology constraints.

Participate in photonic design automation tool development and workflow improvements.

Prepare and manage data for tape-out and support mask review processes.

Debug layout and rule-check issues and propose corrective actions.