We are looking for a talented and experienced Physical Design lead to take part in the physical design and help lead the companys BE activities . This position involves working with external back-end developers as well as carrying out critical tasks in-house, and leading aggressive back-end initiatives to meet challenging targets in terms of area, timing, and layout. In this role, you will be at the center of the companys design efforts and will have a significant influence on our final product.
Responsibilities:
Lead blocks and sub systems execution from RTL to GDSII.
Clearly reflect status and execution metrics and help identify and solve execution bottlenecks.
Spec and define full floor plan, including pin placement, partitions, and power grid.
Develop and validate high-performance, low-power clock network guidelines.
Perform critical block-level place and route and create designs that meet PPA targets.
Review the vendors physical design verification flow at chip and block level and guide other designers on how to fix LVS and DRC violations.
Work with vendors on defining physical design methodologies and assist in flow development for chip.
Requirements:
7+ years of physical design experience, working on complex subsystems.
Experience in leading BE projects, subsystems and or complex high speed blocks.
Experience in leading people (technical and or managerial).
Experience working in advanced node implementation flows.
Good Knowledge of physical design industry standards and practices, including physically aware synthesis, floor planning, CTS, place and route.
Good understanding and experience in physical design verification methodology for debugging LVS and DRC issues at chip and block level.
Proficiency in power delivery, signal integrity, advanced packaging, power projection, and design for low dynamic power.
Working knowledge of extraction and STA methodologies and tools.
Good capabilities of scripting languages, such as Perl, Python and Tcl.
7+ years of physical design experience, working on complex subsystems.
Experience in leading BE projects, subsystems and or complex high speed blocks.
Experience in leading people (technical and or managerial).
Experience working in advanced node implementation flows.
Good Knowledge of physical design industry standards and practices, including physically aware synthesis, floor planning, CTS, place and route.
Good understanding and experience in physical design verification methodology for debugging LVS and DRC issues at chip and block level.
Proficiency in power delivery, signal integrity, advanced packaging, power projection, and design for low dynamic power.
Working knowledge of extraction and STA methodologies and tools.
Good capabilities of scripting languages, such as Perl, Python and Tcl.
This position is open to all candidates.
