The SOC verification group owns the important and challenging job of verifying chip. It is involved from product specification to final SOC delivery, and involves all the system components.
The group is made up of few of the best verification engineers, so besides contributing to making our roads safer, youll get the chance to work at one of the most professional verification teams.
What will your job look like:
You will manage a team of 5 engineers
You'll be responsible for Pre-Silicon system-level verification of the most cutting-edge AI accelerators and technologies in the automotive field.
Define the TestPlan, develop and run tests on simulation/emulation environments, develop test environment and verification collaterals.
You'll have a broad effect on our unique product from the very beginning of the process.
The group is made up of few of the best verification engineers, so besides contributing to making our roads safer, youll get the chance to work at one of the most professional verification teams.
What will your job look like:
You will manage a team of 5 engineers
You'll be responsible for Pre-Silicon system-level verification of the most cutting-edge AI accelerators and technologies in the automotive field.
Define the TestPlan, develop and run tests on simulation/emulation environments, develop test environment and verification collaterals.
You'll have a broad effect on our unique product from the very beginning of the process.
Requirements:
BSc in electrical engineering, computer engineering or computer science
10+ years of experience working in verification environment, tests, and test bench development (C/C++/SV)
TestPlan defining and Coverage-Driven Verification experience
Fullchip/SOC verification experience, strong system understanding
3rd-party IPs integration testing experience
Waveform debugging with the latest EDA tools, root-cause bugs independently
Knowledge in Industry Standard protocols such as AXI/OCP/APB
SW embedded experience, C/C++ skills – Advantage
Strong skills in scripting Perl/Python – Advantage
System Verilog writing skills, preferably in OVM/UVM – Advantage
BSc in electrical engineering, computer engineering or computer science
10+ years of experience working in verification environment, tests, and test bench development (C/C++/SV)
TestPlan defining and Coverage-Driven Verification experience
Fullchip/SOC verification experience, strong system understanding
3rd-party IPs integration testing experience
Waveform debugging with the latest EDA tools, root-cause bugs independently
Knowledge in Industry Standard protocols such as AXI/OCP/APB
SW embedded experience, C/C++ skills – Advantage
Strong skills in scripting Perl/Python – Advantage
System Verilog writing skills, preferably in OVM/UVM – Advantage
This position is open to all candidates.
