Our group is responsible for the development of the company next generation SOC for AI Networking Compute. The development starts from product definition through architecture, design, verification and up to implementation.
The complex SOC is a high-performance device running AI scale-out for inference workloads computer for vision and audio processing, with technologies from multi-disciplines.
In this position you will have end-to-end responsibility for all design flow. In this position you will be responsible for full cluster/block uarch, design, initial synth, lint, integrating and supporting PD, DFT and verification.
If you are curious, innovative, have strong technical skills with a hands-on approach, and understand the full design, system view and SW integration requirements, this position is for you!
The complex SOC is a high-performance device running AI scale-out for inference workloads computer for vision and audio processing, with technologies from multi-disciplines.
In this position you will have end-to-end responsibility for all design flow. In this position you will be responsible for full cluster/block uarch, design, initial synth, lint, integrating and supporting PD, DFT and verification.
If you are curious, innovative, have strong technical skills with a hands-on approach, and understand the full design, system view and SW integration requirements, this position is for you!
Requirements:
7+ years of experience as a VLSI design engineer
B.Sc./M.Sc. degree in electrical/computer engineering from a leading university
Experience in defining uarch and design of complex design units.
SOC design experience.
full cluster/block uarch, design, inital synth, lint, integrating and supporting PD, DFT and verification.
Advantages
Experience in HW implementation of packet processing / Ethernet / Infiniband / RDMA Experience in high-speed interfaces DDR/PCIe – great advantage!
Leading VLSI teams/projects
Verification experience and knowledge with SV/UVM
CPU subsystem multi-core designs experience
Experience with Synthesis and STA analysis
7+ years of experience as a VLSI design engineer
B.Sc./M.Sc. degree in electrical/computer engineering from a leading university
Experience in defining uarch and design of complex design units.
SOC design experience.
full cluster/block uarch, design, inital synth, lint, integrating and supporting PD, DFT and verification.
Advantages
Experience in HW implementation of packet processing / Ethernet / Infiniband / RDMA Experience in high-speed interfaces DDR/PCIe – great advantage!
Leading VLSI teams/projects
Verification experience and knowledge with SV/UVM
CPU subsystem multi-core designs experience
Experience with Synthesis and STA analysis
This position is open to all candidates.
