What you'll be doing:
Define chip interface and silicon interposer interface, focusing on their physical location and netlist.
Develop automation flows for chip integration and power grid implementation.
Perform power integrity analysis of the interposer power grid to ensure flawless performance.
Collaborate with cross-functional teams to successfully implement world-class solutions.
Contribute to the continuous improvement of our integration processes with your innovative ideas and expertise.
A degree in Electrical Engineering or a related field.
2+ years of experience in VLSI physical build and integration flows automation.
Strong knowledge in VLSI build/layout and basic programming/scripting skills.
Familiarity with EDA layout tools such as Cadence Virtuoso, Synopsis Fusion Compiler, or Siemens Calibre.
Advantageous to have experience with UNIX, VBA, TCL, or PERL scripting.
Experience or knowledge in power integrity is a plus.
