Responsibilities:
Develop DFT methodologies for IC designs, such as scan chains, built-in self-test (BIST), boundary scan, MBIST.
Implement and validate DFT features to ensure coverage and quality.
Perform scan insertion, MBIST insertion and ensure architectural spec is met
Generate ATPG patterns for stuck at and at speed, ensure all sequential elements are scannable to achieve high coverage. Generate MBIST patterns and ensure all memories are being covered for defects.
Collaborate with design teams to create test strategies and plans that identify potential defects.
Perform simulations and verification of DFT designs to confirm functionality and accuracy.
Analyze fault models and optimize for high coverage, including stuck-at, transition, and path delay faults.
Collaborate with test engineers to perform yield analysis and improve DFT methodologies.
Troubleshoot and debug design issues found during testing.
Develop techniques to isolate faults and improve test coverage with minimal impact on design.
Work with cross-functional teams (e.g., design, verification, test engineering) to integrate DFT features effectively.
Document DFT architecture, procedures, and test coverage to support production testing and ongoing improvement.
At least 8 years of experience in DFT implementation / methodology is a must.
Strong understanding of digital design and test principles.
Proficiency in DFT techniques, such as scan insertion, BIST, and Automatic Test Pattern Generation (ATPG), MBIST insertion.
Experience with EDA tools (e.g., Synopsys DFT Compiler, Mentor Tessent) and scripting languages (e.g., Python, TCL).
Knowledge of IC design flows, verification tools, and fault models.
Ability to identify, analyze, and resolve testing challenges.
Work effectively within multidisciplinary teams, communicating complex technical details clearly.
Ensure thorough testing, comprehensive fault coverage, and alignment with industry standards.
