Required Physical Design Engineer
About The Position:
We design and builds hardware that fuels disruptive blockchain technologies by accelerating compute performance. Our world-class teams are transforming the future of data, creating the infrastructure that will power the next generation of secure, scalable, green computing. The main bottleneck in scaling cutting-edge solutions in privacy tech, data analysis, and real-time computing is acceleration existing hardware cannot keep up with data processing needs. Our products reshape how data is processed and used on a global scale, and were looking for the brightest people to join us. We are seeking talented and driven individuals to become part of our Yoqneam IC team.
Responsibilities:
Floor Planning Top to Bottom & Bottom up Block level. Exploring different floorplan structures to achieve both the best area & ease of convergence.
Generate high-quality PnR results for one or more digital blocks by applying engineering best practices.
Optimize designs based on key metrics, including power, area, and performance trade-off analyses.
Drive sign-off timing convergence for high-performance designs at the block level, including DRC and LVS signoff
Analyze power integrity (EMIR) results of blocks and apply corrective measures to resolve identified issues.
Collaborating closely with frontend, verification, architecture, physical design, and analog teams.
Work closely with EDA (Electronic Design Automation) vendors on the latest tool feature development and qualification.
About The Position:
We design and builds hardware that fuels disruptive blockchain technologies by accelerating compute performance. Our world-class teams are transforming the future of data, creating the infrastructure that will power the next generation of secure, scalable, green computing. The main bottleneck in scaling cutting-edge solutions in privacy tech, data analysis, and real-time computing is acceleration existing hardware cannot keep up with data processing needs. Our products reshape how data is processed and used on a global scale, and were looking for the brightest people to join us. We are seeking talented and driven individuals to become part of our Yoqneam IC team.
Responsibilities:
Floor Planning Top to Bottom & Bottom up Block level. Exploring different floorplan structures to achieve both the best area & ease of convergence.
Generate high-quality PnR results for one or more digital blocks by applying engineering best practices.
Optimize designs based on key metrics, including power, area, and performance trade-off analyses.
Drive sign-off timing convergence for high-performance designs at the block level, including DRC and LVS signoff
Analyze power integrity (EMIR) results of blocks and apply corrective measures to resolve identified issues.
Collaborating closely with frontend, verification, architecture, physical design, and analog teams.
Work closely with EDA (Electronic Design Automation) vendors on the latest tool feature development and qualification.
Requirements:
BSc or MSc in Electrical Engineering or Computer Engineering.
4+ years experience with physical design.
Expert knowledge of the entire backend design flows from RTL to TO.
Power user of EDA tools from Synopsys (DC/ICC2/FC/PT/STAR-RC/FM), Cadence (EDI/Innovus/Voltus).
Experience in Clock/Power Distribution, P&R, Timing closure, RC Extraction, and physical verification (DRC/LVS) on advanced technology nodes.
Strong, independent and motivated to learn quickly, hard-working, and results oriented.
Good social skills and ability to work collaboratively with other teams.
Advantages:
Experience with high-speed serial interfaces such as PCIe, and DDR.
Experience with low-power design techniques such as multiple power domains, power switches, level shifting, isolation, and dynamic voltage/frequency scaling using Unified Power Format (UPF).
Experience with advanced Engineering Change Order (ECO) techniques including full-layer and metal-only changes
Familiarity with advanced DFT flows & tools.
Strong proficiency in scripting language, such as, Perl, Tcl, Python, Make, and automation methods/algorithms.
BSc or MSc in Electrical Engineering or Computer Engineering.
4+ years experience with physical design.
Expert knowledge of the entire backend design flows from RTL to TO.
Power user of EDA tools from Synopsys (DC/ICC2/FC/PT/STAR-RC/FM), Cadence (EDI/Innovus/Voltus).
Experience in Clock/Power Distribution, P&R, Timing closure, RC Extraction, and physical verification (DRC/LVS) on advanced technology nodes.
Strong, independent and motivated to learn quickly, hard-working, and results oriented.
Good social skills and ability to work collaboratively with other teams.
Advantages:
Experience with high-speed serial interfaces such as PCIe, and DDR.
Experience with low-power design techniques such as multiple power domains, power switches, level shifting, isolation, and dynamic voltage/frequency scaling using Unified Power Format (UPF).
Experience with advanced Engineering Change Order (ECO) techniques including full-layer and metal-only changes
Familiarity with advanced DFT flows & tools.
Strong proficiency in scripting language, such as, Perl, Tcl, Python, Make, and automation methods/algorithms.
This position is open to all candidates.
