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The position
Mobileye EyeC VLSI team – a group designing the chips for Radar and LiDAR systems for ADAS and autonomous cars. The group is responsible for all disciplines of VLSI development, including but not limited to Logic Design, Design Verification, Microarchitecture, Analog and circuit design and layout, Physical and structural design (backend), Product and test engineering.
This unique requisition is for a multi-disciplinary position in the FE design team, which combines VLSI logic design aspects with development and enhancement of design tools, flows and work methodologies.
In this position you will have a cross-project impact on the quality, common methodology and efficiency of the whole design team.
What will your job look like

You will be involved in developing and maintaining common RTL building-blocks which are widely used by the rest of the design team.
Contribute to global design flows and tools – automation, configuration registers infrastructure and chip debug infrastructure.
Explore new tools.
Suggest enhancements which will increase the team’s efficiency, reduce time to market, and reliability of our RTL designs.
All you need is:

BSc in Electrical engineering/Computer Engineering.
At least 3 years of experience in VLSI logic design.
Hands-on programming/scripting experience and passion (Python)
Passion to develop & enhance new tools and flows.
familiarity with tools like CDC, LINT, Power – Advantage.
Familiarity with configuration register flows/tools- – Advantage.
Familiarity with the SW world- Advantage.