Required Experienced Physical Design Engineer
Which department will you join?
VLSI team – a group designing the EyeQ chips for ADAS and autonomous cars.
The group is responsible for all disciplines of VLSI development, including but not limited to Logic Design, Design Verification, Microarchitecture, Analog and circuit design and layout, Physical and structural design (backend), Product and test engineering.
Each Physical Design engineer has an end to end responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & RTL modifications to achieve converges
Were looking for a Backend Engineer to join the growing Physical Design Team, responsible for state of the art SoC design from definition to Tape-Out.
What will your job look like:
Hands-on physical design block owner from RTL to GDS.
Floorplan exploration with guidance and collaboration with front-end and architecture teams.
STA: work with FE and floor planner to manage block and top level constraints and 1st level of timing analysis.
Synthesis exploration and final synthesis netlist: Scan insertion @ synthesis, clean checks from Lint, UPF & Spyglass.
Place & Route: from Synthesis netlist to final layout and signoff verification with target to achieve best power performance and area.
Which department will you join?
VLSI team – a group designing the EyeQ chips for ADAS and autonomous cars.
The group is responsible for all disciplines of VLSI development, including but not limited to Logic Design, Design Verification, Microarchitecture, Analog and circuit design and layout, Physical and structural design (backend), Product and test engineering.
Each Physical Design engineer has an end to end responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & RTL modifications to achieve converges
Were looking for a Backend Engineer to join the growing Physical Design Team, responsible for state of the art SoC design from definition to Tape-Out.
What will your job look like:
Hands-on physical design block owner from RTL to GDS.
Floorplan exploration with guidance and collaboration with front-end and architecture teams.
STA: work with FE and floor planner to manage block and top level constraints and 1st level of timing analysis.
Synthesis exploration and final synthesis netlist: Scan insertion @ synthesis, clean checks from Lint, UPF & Spyglass.
Place & Route: from Synthesis netlist to final layout and signoff verification with target to achieve best power performance and area.
Requirements:
BSc or MSc degree in Computer Engineering or Electrical Engineering.
5+ years of experience in physical design.
Experience in scripting languages like Tcl/python/Perl/tcsh.
Team player with excellent communication skills, customer orientation, and a can-do attitude.
Experience in relevant domains – Advantage.
Building or maintaining implementation tools and flow Advantage.
BSc or MSc degree in Computer Engineering or Electrical Engineering.
5+ years of experience in physical design.
Experience in scripting languages like Tcl/python/Perl/tcsh.
Team player with excellent communication skills, customer orientation, and a can-do attitude.
Experience in relevant domains – Advantage.
Building or maintaining implementation tools and flow Advantage.
This position is open to all candidates.
