Will you help us design future generations of revolutionary products? Are you an engineer with a strong foundation and real passion for building new technologies? Do you have track record leading DFT efforts for complex chip designs? Imagine what you could do here. new ideas have a way of becoming excellent products, services, and customer experiences very quickly. Every single day, people do amazing things . Do you want to impact billions of users by developing extraordinary products with a prime focus on accuracy and performance of the product? You will become part of a hands-on development team that furthers engineering excellence, creativity and innovation.
Dynamic, inspiring people and innovative technologies are the norm here. We want you to join our team if you are an innovative engineer with the dream to research and develop solutions that do not yet exist. In this highly visible role, you will be at the centre of a System-on-Chip design effort. collaborating with all disciplines, with a critical impact on getting functional products to millions of customers quickly.
Description
Lead the complete DFT solutions in a chip design by working with chip DFT team to document DFT specifications, and define the SoC test interface Develop and implement DFT architecture Work with the validation team to verify DFT implementations and implement design changes Generate structural test vectors, analyze and improve coverage Work with designers on STA, physical, power and logical issues Work with Test Engineers to bring up test vectors on silicon.
Dynamic, inspiring people and innovative technologies are the norm here. We want you to join our team if you are an innovative engineer with the dream to research and develop solutions that do not yet exist. In this highly visible role, you will be at the centre of a System-on-Chip design effort. collaborating with all disciplines, with a critical impact on getting functional products to millions of customers quickly.
Description
Lead the complete DFT solutions in a chip design by working with chip DFT team to document DFT specifications, and define the SoC test interface Develop and implement DFT architecture Work with the validation team to verify DFT implementations and implement design changes Generate structural test vectors, analyze and improve coverage Work with designers on STA, physical, power and logical issues Work with Test Engineers to bring up test vectors on silicon.
Requirements:
3+ years of DFT experience, leading DFT efforts for complex chip designs
We are counting on your expertise and knowledge about industrial standards and practices in DFT – including ATPG, JTAG, MBIST and trade-offs between test quality and test time
You have experience developing DFT specifications and driving DFT architecture and methods for designs
You are confident with Verilog and / or VHDL, and have experience with simulators and waveform debugging tools
By now you are demonstrating proven understanding of design verification (DV) methodologies for validating DFT implementation in simulation pre-silicon
You can debug ATPG patterns, compressed ATPG patterns, MBIST, and JTAG/1500 related issues
You have experienced with STA constraints development and analysis for DFT modes and SDF simulations
You love conducting experiments during silicon debug, gathering and analyzing data; and utilize scripting to support efficient handling of ATE data
Preferred Qualifications
BS.c/ MS.c in EE/ CE
3+ years of DFT experience, leading DFT efforts for complex chip designs
We are counting on your expertise and knowledge about industrial standards and practices in DFT – including ATPG, JTAG, MBIST and trade-offs between test quality and test time
You have experience developing DFT specifications and driving DFT architecture and methods for designs
You are confident with Verilog and / or VHDL, and have experience with simulators and waveform debugging tools
By now you are demonstrating proven understanding of design verification (DV) methodologies for validating DFT implementation in simulation pre-silicon
You can debug ATPG patterns, compressed ATPG patterns, MBIST, and JTAG/1500 related issues
You have experienced with STA constraints development and analysis for DFT modes and SDF simulations
You love conducting experiments during silicon debug, gathering and analyzing data; and utilize scripting to support efficient handling of ATE data
Preferred Qualifications
BS.c/ MS.c in EE/ CE
This position is open to all candidates.
