We are looking for a Senior Verification engineer to be a significant part in developing a complex and innovative SOC chip in a start-up company. Taking full ownership of entire domain, defining the verification strategy, writing, and executing verification plan in system Verilog UVM. About Us:VLSI group is responsible for the development of next generation … Read more
Be part of a team to verify complex digital design blocks at subsystem level or full chip level by fully understanding the design specification and interacting with design engineers to identify key verification scenarios.Create and enhance constrained-random verification environments using UVM SystemVerilog or create complex multi core based C tests using reusable C test libs.Identify … Read more
Participate in evaluation of future ASIC designs and general architecture for executing Googles data center networking roadmap, off-the-shelf components, vendor co-developments, custom designs, and chiplets.Collaborate in developing new layer protocols for data center networking.Understand how everything interacts with software and other ASIC subsystems to implement groundbreaking data center networks.Define performance hardware/software interfaces. Write micro-architecture and … Read more
Define architecture and micro-architecture features, write specifications, and understand implementation tradeoffs (e.g., performance, power, frequency, etc.).Define the CPU block level design document (e.g., interface protocol, block diagrams, transaction level flow, control registers, pipelines, etc.).Perform RTL development process (e.g., coding and debug in Verilog, SystemVerilog, or VHDL), function/performance simulation debug, and Lint/CDC/FeV/PowerIntent checks.Contribute to the SoC … Read more
Participate in evaluation of future ASIC designs and general architecture for executing Googles data center networking roadmap, off-the-shelf components, vendor co-developments, custom designs, and chiplets.Collaborate to develop new layer protocols for data center networking.Understand how everything interacts with software and other ASIC subsystems to implement data center networks.Define performance hardware/software interfaces. Write micro-architecture and design … Read more
Plan the verification of digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.Create and enhance constrained-random verification environments using SystemVerilog or formally verify designs with Strategic Value Add (SVA) and industry leading formal tools.Identify and write all types of coverage measures for stimulus and corner-cases.Debug tests … Read more
Plan the verification of digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.Create and enhance constrained-random verification environments using SystemVerilog or formally verify designs with Strategic Value Add (SVA) and industry leading formal tools.Identify and write all types of coverage measures for stimulus and corner-cases.Debug tests … Read more
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.Create and enhance constrained-random verification environments using SystemVerilog or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools.Identify and write all types of coverage measures for stimulus and corner-cases.Debug tests … Read more
Contribute to CPU front-end designs, emphasizing micro-architecture and RTL design for next generation CPU.Propose performance enhancing micro-architecture features with efficiency in mind. Work with architects and performance teams for trade-off studies.Deliver designs that meet power, performance, and area (PPA) goals with production quality.Interpret techniques into design constructs and languages in order to provide guidance to … Read more
Execute activities in the design, implementation, and verification of Design for Testing solutions for Application-Specific Integrated Circuit (ASICs).Develop DFT strategy for hierarchical DFT, Scan, and Automatic Test Pattern Generation (ATPG).Perform ATPG scan, cover debug and motivate design fixes for coverage and quality improvements.Perform scan verification at Register-Transfer Level (RTL) and gate level.Work with other Engineering … Read more
