Key job responsibilities:
* Daily involvement in all aspects of physical design chip development (RTL2GDS), including floorplanning, synthesis, clock tree synthesis, place and route, static timing analysis, power and noise analysis, physical verification testing, and equivalence checks.
* Being actively engaged in design-backend convergence aspects and defining timing constraints.
* Taking full end-to-end responsibility for the physical design of macros and clusters level, according to specifications, under challenging constraints, with focus on optimizing power, area, and performance.
* Participation in the development of design flows, using a variety of EDA tools and vendors such as Synopsis and Cadence.
* Engaged in defining implementation and signoff methodologies.
BASIC QUALIFICATIONS:
– 8+ years of experience.
– Understanding the entire place and route flow (RTL to GDS).
– Very deep understanding of timing.
– Process and technology oriented.
– Leadership and mentoring skills.
– Experience in advanced nodes technologies.
PREFERRED QUALIFICATIONS:
– Bachelor’s degree in computer science or equivalent.
