Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of platforms, we make product portfolio possible. We’re proud to be our engineers’ engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
Define the block level design document such as interface protocol, block diagram, transaction flow, pipeline etc.
Perform RTL development (i.e., coding and debug in Verilog, SystemVerilog), function/performance simulation debug and Lint/CDC/FV/UPF checks.
Develop a flow for CDC/RDC and assimilate hierarchically in the organization and Write SDC and Run synthesis.Be able to debug timing/power and support ASIC silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Communicate and work with multi-disciplined and multi-site teams.
Bachelor’s degree in Electrical Engineering, Computer Engineering, or
equivalent practical experience.
Experience in ASIC development with Verilog/SystemVerilog, VHDL.
Experience in logic design and debug.
Experience with ASIC design verification, synthesis, timing/power analysis, or DFT.
Preferred qualifications:
Knowledge of high performance and low power design techniques.
Knowledge of SOC architecture.
Knowledge of assertion-based formal verification.
Knowledge in one of these areas: PCIe, DDR, AXI, ARM processors family.
Proficiency with a scripting language like Tcl, Python or Perl.
