Description:
You will develop verification test plans, test benches, tools and infrastructure, protocol monitors and agents, and coverage driven stimulus.
Apply advanced techniques to achieve verification with the highest quality, productivity, and time-to-market.
Apply deep system level understanding to find system architecture bugs, verifying the DUT at multiple levels – from block level to the entire IP and subsystem, with additional emphasis on power (NLP) and performance.
You will work closely with the design and architecture teams from the early stages of feature definition, to ensure timely delivery of quality designs.
Working with methods to accelerate verification time.
Involvement with Post Silicon Validation and other verification teams.
Candidate should have good interpersonal and collaboration skills, to work with our partner Design and Architecture teams
Key Qualifications:
+2 years experience in SoC Verification, media IP verification experience is a plus.
You will need to have advanced knowledge of SoC/Media IP architecture/design & in-depth knowledge of verification flow.
Expected to have a deep understanding and shown experience in advanced verification process, including dynamic and coverage based.
Familiarity with verification environments, UVM, SystemVerilog an advantage.
Knowledge of hardware acceleration an advantage.
Scripting and programming experience using several of the following: Python, Perl, e, SystemVerilog, C++, and TCL.
Education & Experience:
B.Sc / M.Sc in Electrical or Computer Engineering.
