we are looking for a Formal Verification Engineer, Networking, Google Cloud
Responsibilities
Plan the formal verification strategy and create the properties and constraints for digital design blocks.
Utilize formal property verification tools combined with formal verification closure techniques to verify properties.
Contribute improvements to methodologies to enhance formal verification results.
Architect and implement reusable formal verification components.
Responsibilities
Plan the formal verification strategy and create the properties and constraints for digital design blocks.
Utilize formal property verification tools combined with formal verification closure techniques to verify properties.
Contribute improvements to methodologies to enhance formal verification results.
Architect and implement reusable formal verification components.
Requirements:
Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
4 years of experience working in main interconnects, Direct Memory Access (DMA), controllers, and power management.
Experience capturing design specification in a temporal assertion language (e.g., System Verilog Assertions (SVA) or Property Specification Language (PSL)).
Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
4 years of experience working in main interconnects, Direct Memory Access (DMA), controllers, and power management.
Experience capturing design specification in a temporal assertion language (e.g., System Verilog Assertions (SVA) or Property Specification Language (PSL)).
Preferred qualifications:
Master's degree or PhD in Electrical Engineering or Computer Science, or a related field.
Experience working with one or more formal verification tools (e.g., JasperGold, VC Formal, Questa Formal, or Display and Video 360).
This position is open to all candidates.
