Required Senior ASIC Frontend Design Engineer
About The Position
We design and build hardware that fuels disruptive blockchain technologies by accelerating compute performance. Our world class teams are transforming the future of data, creating the infrastructure that will power the next generation of secure, scalable, green computing. The main bottleneck in scaling cutting edge solutions in privacy tech, data-analysis and real-time computing is acceleration existing hardware cannot keep up with data processing needs. Our products reshape how data is processed and used on a global scale, and were looking for the brightest people to join us. We are looking for talented and ambitious individuals to join our Yoqneam IC team.
Responsibilities:
We offer the opportunity to join our growing frontend design team.
Join a team of VLSI frontend design engineers in our projects.
Define, plan and implement our next chip in our on-going product line and in a new product line of cryptography algorithms acceleration SoCs.
Work closely with multiple teams within organizations such as Architecture, BE, Circuit, Analog and FW
Responsible for scaling up the frontend design environment methodologies.
About The Position
We design and build hardware that fuels disruptive blockchain technologies by accelerating compute performance. Our world class teams are transforming the future of data, creating the infrastructure that will power the next generation of secure, scalable, green computing. The main bottleneck in scaling cutting edge solutions in privacy tech, data-analysis and real-time computing is acceleration existing hardware cannot keep up with data processing needs. Our products reshape how data is processed and used on a global scale, and were looking for the brightest people to join us. We are looking for talented and ambitious individuals to join our Yoqneam IC team.
Responsibilities:
We offer the opportunity to join our growing frontend design team.
Join a team of VLSI frontend design engineers in our projects.
Define, plan and implement our next chip in our on-going product line and in a new product line of cryptography algorithms acceleration SoCs.
Work closely with multiple teams within organizations such as Architecture, BE, Circuit, Analog and FW
Responsible for scaling up the frontend design environment methodologies.
Requirements:
BSc or MSc in Electrical Engineering or Computer Engineering
8+ years of VLSI experience.
Experience with multi clock domain, multi power domain designs (UPF).
Methodologic approach.
Strong Motivated to learn quickly, hard-working, and is results-oriented.
Great interpersonal relations skills.
How to Stand Out:
Networking design experience Major Advantage
Backend experience: STA tools, formal equivalence tools, frontend/backend handoff methodologies.
SoC design/Integration experience.
Proven Methodologies and Environmental Building Experience.
Strong proficiency in scripting language, such as, Perl, Tcl, Python, Make, and automation methods/algorithms.
BSc or MSc in Electrical Engineering or Computer Engineering
8+ years of VLSI experience.
Experience with multi clock domain, multi power domain designs (UPF).
Methodologic approach.
Strong Motivated to learn quickly, hard-working, and is results-oriented.
Great interpersonal relations skills.
How to Stand Out:
Networking design experience Major Advantage
Backend experience: STA tools, formal equivalence tools, frontend/backend handoff methodologies.
SoC design/Integration experience.
Proven Methodologies and Environmental Building Experience.
Strong proficiency in scripting language, such as, Perl, Tcl, Python, Make, and automation methods/algorithms.
This position is open to all candidates.
