כדי לראות תפקידים מתאימים עליך להוסיף כישורים בפרופיל האישי במערכת COB.
ההרשמה והשימוש חינם!
מעולה, רוצה להירשם
ASIC / VLSI|הנדסה|חשמל ואלקטרוניקה|מהנדס חשמל|מהנדס מחשבים|תוכנה
חיפה
פורסם לפני יותר מחודשיים
פורסמה ברשת
As a Chip Infrastructure Engineer, you will plan and execute work in an innovative and fast-paced environment, with a focus on infrastructure that enables design and verification teams to produce the chips that power computing needs. You'll be part of the chip infrastructure team responsible for compute, storage, common chip design components, and front-end tool flows.

In this role, you will work with architects, logic designers, and verification engineers to develop flows to build and verify SoC chip designs. Youll also work closely with software, physical design, silicon bring-up and validation teams to enable a successful software integration, implementation, silicon bringup and deliver quality silicon.
Responsibilities
Work with partner teams to provide the compute, storage and methodology needs of the chip design, verification and physical design teams.
Collaborate with Application-Specific Integrated Circuit (ASIC) teams to implement tools and methodologies.
Design and implement CAD tools, solutions and methodologies for ASIC development.
Extend the capabilities of third-party tools through their dedicated APIs.
Provide documentation, training, and support to increase end user productivity.

Requirements:
Bachelors degree in Electrical Engineering, Computer Science, or equivalent practical experience.
Experience in scripting languages (e.g., Unix Shell, Python) to build tools and flows.
Experience with software version control systems (e.g., Git, Mercurial), and concepts of branches, commits, and merges.
Experience working with cross-functional teams for quality tape-outs.

Preferred qualifications:
Experience with ASIC design, debug, and verification flows.
Experience evaluating multiple vendor solutions and driving tool decisions/design improvements.
Experience with design verification techniques, including constrained-random simulation, formal property verification, or static verification.
Experience working with Register-Transfer Level (RTL) teams and design integration methodologies that improve team productivity and velocity.

This position is open to all candidates.
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