You will play a key role in building and leading our physical design team, developing flows and methodologies, and driving the full RTL-to-GDSII implementation and signoff for one of the most advanced SoCs in the industry.
What Youll Do
Take part in shaping methodology and best practices in advanced technologies
Drive end-to-end implementation: synthesis, P R, timing closure, and signoff
Collaborate closely with architecture and design teams on timing, floorplaning, partitioning, and power specification
Define and optimize static timing constraints, area, and power goals at block and top levels
Take part in flow development and automation to improve efficiency and quality of results
At least 3+ years experience with RTL2GDS flow
BSC/MSC in Electrical/Computer engineering
Deep understanding on STA principals, synthesis, and P R flow
Solid experience in physical verification and advanced process nodes
Advantages:
Top level implementation and signoff
Experience with DFT
Managerial experience
