The ideal candidate is execution-driven, innovative, and passionate about building high-performing team and cutting-edge AI technology.
Responsibilities
Manage and lead a team of Front-End Design engineers.
Be accountable for the teams development lifecycle, including architecture, development, validation, and release, focusing on meeting PPAA targets.
Lead development of advanced VLSI IPs for AI processors, DSP and HW accelerators while continuing pushing the VLSI design methodologies, procedures, sign off and AI tools assimilation to its next level.
Support system bring-up, debugging, and customer-facing activities when needed
B.Sc. in Electrical Engineering, or related field.
10 years of experience in Verilog/SV and Front-End design development.
3+ years leading a team of engineers.
Experience managing multiple I/F with different groups within the company.
Strong understanding of HW/SW interaction and system architecture.
Superb knowledge in VLSI development on all if its aspects – VLSI Design, Verification, CAD, Emulation and Back end facing incredible challenges in PPAA targets.











